Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device including a bit line.
A semiconductor memory device includes a memory array. Memory cells included in the memory array may be divided into memory blocks. To perform an operation related to data input/output to/from the memory cells, operation voltages needed for the data input/output operation should be supplied to a selected memory block.
To supply the operation voltages to the selected memory block of the memory blocks, a row decoder for generating block select signals according to a row address signal and voltage transferring circuits for transferring the operation voltages to the selected memory block according to block select signals are required.
Since the memory array includes a plurality of memory blocks, the block select signals corresponding to number of the memory blocks should be generated to select one of the memory blocks. Accordingly, a circuit for embody the row decoder has become complex, and an area occupied by the row decoder in a chip has increased.
High voltage may be required for the data input/output to/from the memory cells. Accordingly, the voltage transferring circuits should have high voltage transistors being capable to operate at high voltage. Size of the high voltage transistors is greatly larger than that of normal transistors. Since each of the memory blocks is provided with the voltage transferring circuit, an area by which the voltage transferring circuits occupy is considerably burdensome.
As a result, an area by which a peripheral circuit occupies increases accordingly as the number of the memory block increases, and thus size of the chip also increases.